MCV | ARIES Embedded GmbH

MCV offers the full flexibility of the Altera Cyclone V SoC FPGA family. It integrates an ARM-based hard processor system (HPS) consisting of processor, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. The Altera SoCs combine the performance and power savings of hard intellectual property (IP) with the flexibility of programmable logic.

MCV features additional hard logic such as PCI Express® Gen1, multiport memory controllers, and high-speed serial transceivers. Our SoCs drive down power and cost while enabling performance levels required by cost-sensitive applications.

Due to the flexibility of the MCV concept 25KLE, 40KLE, 85KLE and 110KLE SoC FPGAs are supported by MCV.

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Features

Altera Cyclone V SoC FPGA

without PCIe support

A2: 5CSEBA2U23C8N
25KLE, 36 DSP blocks
A4: 5CSEBA4U23C7N
40KLE, 58 DSP blocks
A5: 5CSEBA5U23C7N
85KLE, 87 DSP blocks
A6: 5CSEBA6U23C7N
110KLE, 112 DSP blocks

with PCIe support

A2: 5CSXFC2C6U23C7N
25KLE, 36 DSP blocks, 6 transceivers 2.5Gbit/s
A4: 5CSXFC4C6U23C7N
40KLE, 58 DSP blocks, 6 transceivers 2.5Gbit/s
A5: 5CSXFC5C6U23C7N
85KLE, 87 DSP blocks, 6 transceivers 2.5Gbit/s
A6: 5CSXFC6C6U23C7N
110KLE, 112 DSP blocks, 6 transceivers 2.5Gbit/s

Dual 800 MHz Cortex A9 Cores
HPS-Peripherals
1 GByte DDR3 RAM
256 Mbit configuration device
4GByte eMMC memory
143 FPGA signals
66 HPS signals
Clock distribution
default configuration:

Gigabit Ethernet
UART
CAN
SPI
I²C
USB

additional interfaces would be optionally available such as

one or more display controller
second Gigabit Ethernet
CAN, SPI, I²C,
camera port
DSP blocks
microcontroller

single 3,3V supply
size 74mmx42mm
2 x Samtec QSH-090-01-F-D-A board-to-board interconnect

Block Diagram

Pictures

Order Codes

MCV-2DB

5CSEBA2U23C8N

25 KLEs
36 DSP Blocks
145 FPGA I/O
181 HPS I/O

Dual CortexA9 SoC FPGA, Altera
600MHz speed
1GB DDR3 SDRAM
4GByte eMMC
size 74mm x 42mm
2 x Samtec QSH-090-01-F-D-A board-to-board interconnect
0°C...+70°C

MCV-6DB

5CSEBA6U23C7N

110 KLEs
112 DSP Blocks
145 FPGA I/O
181 HPS I/O

Dual CortexA9 SoC FPGA, Altera
800MHz speed
1GB DDR3 SDRAM
4GByte eMMC
size 74mm x 42mm
2 x Samtec QSH-090-01-F-D-A board-to-board interconnect
0°C...+70°C

MCV-X2DB

5CSXFC2C6U23C7N
- 25 KLEs
- 36 DSP Blocks
- 2 x PCIe Hard IP Block, 6 transceiver, 3.125 GBps
- 145 FPGA I/O
- 181 HPS I/O
Dual CortexA9 SoC FPGA, Altera
800MHz speed
1GB DDR3 SDRAM
4GByte eMMC
size 74mm x 42mm
2 x Samtec QSH-090-01-F-D-A board-to-board interconnect
0°C...+70°C

MCV-X6DB

5CSXFC6C6U23C7N

110 KLEs
112 DSP Blocks
2 x PCIe Hard IP Block
9 transceiver, 3.125 GBps
145 FPGA I/O
181 HPS I/O

Dual CortexA9 SoC FPGA, Altera
800MHz speed
1GB DDR3 SDRAM
4GByte eMMC
size 74mm x 42mm
2 x Samtec QSH-090-01-F-D-A board-to-board interconnect
0°C...+70°C

MCV- versatile usability at its best

MCV is of course one of the most flexible System on Module in the embedded market. Thanks to the combination of the Dual Cortex A9 HPS with the FPGA part most application can be addressed with this approach:

MCV combines FPGA and CPU

MCV connects the world of FPGA projects with common CPU architecture hardware. A's service is to provide a flawless integration of both areas so that users can focus on the development of application software and/or dedicated FPGA-IP

High Flexibility

Maximum flexibility for using the SoM with 'exotic' interface requirements. Combining standard IP cores like i.e. display-controller, Ethernet, CAN, serial, I²C, SPI, etc, unique SoM configurations can be used. Benefit from the variety of freely available IP-cores by Altera, or, create your own.

Plug and Play

The SoM supports mainline software for U-Boot and Linux. The BSP covers the entire HPS part of the SoC FPGA. A supplies software development services for drivers, bootloaders and their integration for MCV.
Your SoC FPGA projects starts in a few minutes

Robust and Reliable

High-quality connector suitable for high frequency signals and applications in harsh environments. Use a well designed System on Module with sufficient ressources in terms of performance, interfaces and memory

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